1. Field of the Invention
This invention pertains to a broadband exchange and more particularly to a controller for distributing loads among a plurality of call processors for controlling a switching network used in a broadband exchange per an asynchronous transmission mode.
2. Description of the Related Art
With the widespread use of data communication, public switched networks are now required to provide high-quality data communication, as well as the traditional voice communication.
Broadband ISDN (B-ISDN) has begun to be utilized for communication networks not only for low-speed data, such as voice data, but also for high-speed data, such as moving images, and various interfaces have been standardized. Unlike the traditional switching method, a B-ISDN utilizing an asynchronous transmission mode (ATM) can commonly carry at different speeds various sorts of information, e.g. voice data, moving image data and even continuous information mixed with bursty information.
An ATM communication network transmits and exchanges information of different bands divided and housed in fixed-length data units called cells, instead of in variable-length packets as in traditional packet communication. Cells containing channel data and packet data are indiscriminately multiplexed, transmitted over optical fibers at high speed, and rapidly exchanged by hardware switches. Thus, an ATM communication network can offer flexible service requiring different transmission speeds and makes efficient uses of transmission paths.
As described above, user information is divided into several pieces according to its length and cells are configured by adding headers, e.g. of a few bytes, to respective data, e.g. of 32 to 120 bytes, comprising the divided pieces of information. A header contains a virtual channel identifier (VCI) for identifying the originating user of the corresponding data. Thus, user information stored in cells is multiplexed over ATM highways and transmitted and exchanged to a destined terminal.
An exchanger adds to input cell information as to how they should be exchanged in the exchange system, so that they are autonomously transmitted over a transmission path in the exchange network with their added header information read by respective switches in the exchanger. Hence, this switching method is called a self-routing method, and the group of switches within the exchanger is called a self-routing part.
FIG. 1 shows an exemplary configuration of a multistage self-routing part (MSSR) being a switching part in an ATM exchanger. The MSSR comprises plural [generally three (3)] stages of self-routing modules (SRMs) each comprising a plurality of input and output terminals. An ATM exchanger is equipped with two such MSSRs, as shown in FIG. 1, for both directions of data transmission.
FIG. 2 shows an exemplary configuration of an SRM shown in FIG. 1. An SRM has pluralities of input and output lines, and a crossing point of an input line and an output line is provided with a buffer. In FIG. 2, the SRM has four (4) input lines, four (4) output lines and sixteen (16) buffers at respective crossing points.
As described earlier, at the entrance of an MSSR, the respective input cells have added to themselves information, called tag information, as to which input line they are input to and which output line they are output from. Thus, tag information routes cells in an MSSR. For instance, when SRMs are connected in three (3) stages as shown in FIG. 1 and respective SRMs have four (4) output lines as shown in FIG. 2, respective input cells have added to themselves 6-bit tags comprising three (3) sets of 2-bit tags specifying which of the four (4) output lines is selected for outputting corresponding to the three (3) SRM stages.
Meanwhile, as described earlier, the header of each input cell has added to itself a VCI for identifying the originating user of the cell. This VCI is defined for respective logical links among exchangers. Therefore, the header of an input cell from an originating user has added to itself the VCI specifying the link with the exchanger of the preceding stage, over which link the cell is transmitted. The respective exchangers replace the VCI added to the header of an input cell with the new VCI specifying the link with the exchanger of the succeeding stage, over which link the cell is transmitted. Thus, cells are sequentially transmitted to a plurality of exchangers towards a destined terminal.
A part called a Virtual Channel Converter (VCC) in the MSSR of an exchanger performs the above two processes, i.e. replacing VCIs and adding tag information, for the input cells. The new VCI for replacing the old VCI attached to an input cell and the new tag information for replacing the old tag information are uniquely determined by the old VCI. Accordingly, a VCC is provided with a conversion table enabling it to obtain, from the old VCI of an inputted cell, the new VCI to be added to the input cell when it is output and the tag information.
When a user originates a call, a call processor determines, based on the traffic condition in the entire ATM network, the content of a VCC conversion table for obtaining, from the old VCI, the appropriate tag information and the new VCI, which specify the optimal transmission path for the cells of the originated call. Hence, the larger the MSSR and the more SRM stages it contains, the more complex the processes the call processor must perform.
As such, if one call processor performs all the processes for all incoming calls, which is ordinarily considered for all processings, the network's response degrades.
An ordinary solution to such a problem is to distribute load among a plurality of call processors. However, there has been no known load distribution controlling method for effectively controlling MSSRs comprising plural stages of SRMs. When an MSSR comprises three (3) SRM stages, for instance, three (3) processors may share the switching control in respective stages. However, since the switch loads in respective stages are not uniform, a crucial problem still remains as to how efficiently a switching can be performed by distributing loads equally among all call processors.